Paper 3. STTRAM Scaling and Retention Failure

Ever larger on-die memory arrays for future processors in CMOS logic
technology drive the need for dense and scalable embedded memory
alternatives beyond SRAM and eDRAM. Recent advances in nonvolatile
spin transfer torque (STT) RAM technology, which stores data by the spin
orientation of a soft ferromagnetic material and shows current induced
switching, have created interest for its use as embedded memory. Any attractive
memory technology would be a viable solution if it could scale well for a few
generations. We study the STTRAM scaling roadmap for last level cache
(LLC) and how much dimensional scaling is feasible with this technology.

This article will show that the main limitation on STTRAM dimensional scaling
will be posed by retention time failure. When an STTRAM cell is scaled,
the thermal stability factor (D) scales down linearly with the area, and causes
unreliability due to retention failure. Today manufacturing techniques can
fabricate nonvolatile STTRAM cells (with D ≥ 60 kT). Researchers are actively
working at two fronts to pave the STTRAM scaling path for a few generations:
1) Novel manufacturing techniques that can facilitate fabrication of nonvolatile
STTRAM cells (with D ≥ 60 kT), 2) Architecture solutions that can
relax the non-volatility condition and drop the required lower bound of 60 kT.
In this article, we focus on the solutions in the second category, that is, relaxing
the nonvolatility condition to allow lower bound on D. Although there have
been an extensive number of publications on dramatically relaxing the D, we
believe these solutions alone can lower the bound on the thermal stability down
one more generation before they become too costly. Beyond one more generation
scaling, the dimensional scaling would depend on new manufacturing techniques
to fabricate STTRAM cells with high thermal stability at scaled dimensions.

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