Integrated circuit processing technology and computer architectures continue to mature. Single chip CPUs have been demonstrated to exceed one TeraFLOP. This high level of computation, concentrated in a small area, creates many system design challenges. One of these major challenges is designing and building a memory sub-system that allows these CPUs to perform well while staying within reasonable system cost, volume, and power constraints.
This article describes the challenges that tera-scale computing presents to the memory sub-system, such as performance metrics including memory bandwidth capacity and latency, as well as the physical challenges of packaging and memory channel design. New technologies that need to be developed and matured for tera-scale memory sub-systems are also discussed.