Intel Xeon Phi Coprocessor High Performance Programming, 1st Edition

Book Type: Related Books
Category: Programming

Authors Jim Jeffers and James Reinders spent two years helping educate customers about the prototype and pre-production hardware before Intel introduced the first Intel Xeon Phi coprocessor. They have distilled their own experiences coupled with insights from many expert customers, Intel Field Engineers, Application Engineers and Technical Consulting Engineers, to create this authoritative first book on the essentials of programming for this new architecture and these new products.

This book is useful even before you ever touch a system with an Intel Xeon Phi coprocessor. To ensure that your applications run at maximum efficiency, the authors emphasize key techniques for programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi coprocessors, or other high performance microprocessors. Applying these techniques will generally increase your program performance on any system, and better prepare you for Intel Xeon Phi coprocessors and the Intel MIC architecture.

"This book belongs on the bookshelf of every HPC professional. Not only does it successfully and accessibly teach us how to use and obtain high performance on the Intel MIC architecture, it is about much more than that. It takes us back to the universal fundamentals of high-performance computing including how to think and reason about the performance of algorithms mapped to modern architectures, and it puts into your hands powerful tools that will be useful for years to come."

Robert J. Harrison, Institute for Advanced Computational Science, Stony Brook University

“This book provides the definitive reference on the Xeon Phi architecture, from the “insiders” with more experience on the platform than anyone else alive. Nothing is going to be more important to the future of computing performance over the next few years than the emerging dominance of many-core platforms. With this book, the authors make the architecture and programming models for Intel’s many-core approach accessible to everyone.”    

Dan Stanzione, Deputy Director, Texas Advanced Computing Center, The University of Texas at Austin

“The authors’ consummate knowledge of the architecture shines through in this excellent introduction to the fundamentals of programming for the Intel® Xeon Phi™ coprocessor.” I highly recommend this engaging treatise to programmers interested in effectively utilizing the Intel® Xeon Phi™ coprocessor.”

R. Glenn Brook, Ph.D., Chief Technology Officer, Joint Institute for Computational Sciences, Director, Application Acceleration Center of Excellence, University of Tennessee / Oak Ridge National Laboratory

About the Author(s)

James Reinders

James Reinders is a senior engineer who has spent the past 16 years at Intel Corporation working on projects such as the world's first TeraFLOP supercomputer (ASCI Red) and on the compilers and architectures for the Pentium® Pro, Pentium II, Itanium®, Pentium® 4, and iWarp processors. James is currently the director of business development and marketing for Intel's Software Products Division and serves as the division's chief product evangelist.

Jim Jeffers

Jim Jeffers is a senior engineer in Intel’s Technical Computing Group focused on enabling customers with Intel MIC architecture products.  He has over 25 years of experience in design, implementation and technical team leadership for high performance computing and multimedia products. As a member of the foundational Intel MIC architecture team, Jim helped define the product roadmap and led the initial phases of the device software stack development and the software performance team. Jim’s notable prior work includes contributing to the development of the imaging technology behind the virtual ‘first down line’ on American football TV broadcasts.  Jim has three granted US patents.