Intel® Xeon Phi™ Coprocessor Micro Architecture and Tools

Design and Development
Book Type: Related Books
Category: Programming
Table of Contents:

Technical computing has become an integral part of research and development of new technologies in modern civilization. It is used in industry and academia equally to produce new products, produce weather forecasting, geosciences exploration, financial modeling, car crash simulation, electro-magnetic field propagation from mobile phones etc. Massively parallel processors like Intel® MIC architecture has been developed to increase the computational power to remove these research barriers. This book is targeted to give the readers an in-depth look at the MIC processor architecture, parallel data structure and algorithm used by various Technical Computing applications that will be suitable for such a coprocessor.

"This book is ideal for programmers ready to understand the low-level architecture of the Intel MIC.  It is a complete reference guide for developing operating system components, highly optimized run-time layers, and efficient math libraries that can leverage the tremendous power of the Intel MIC.  The author has done an excellent job of covering details such as the micro architecture, memory, and power management."

Peter Beckman, Director, Exascale Technology & Computing Institute, Argonne National Laboratory

“This book provides a comprehensive discussion of the PHI architecture and tools, with detailed diagrams and examples that provide both breadth and depth. It is a must-have for anyone who wants to understand and prepare for the future of high-performance computing.”

Michael Heroux, Distinguished Technical Staff, Sandia National Laboratories

“I believe that the Intel® Xeon Phi™ many-core co-processor will be an important milestone for exascale computing. This book covers a comprehensive set of descriptions about Xeon Phi in detail, including vector and core micro-architecture, cache and memory system, data transfer, power management and many-core programming with a variety of examples. It is also interesting that the upcoming OpenMP 4.0 is adopted as an offload extensions in Xeon Phi programming. I highly recommend this book as good reading for researchers, engineers, and graduate students who study advanced high performance computing.”

Mitsuhisa Sato, Professor, University of Tsukuba

About the Author(s)

Reza Rahman

Reza Rahman is a Senior Staff Engineer in Intel's Software and Services Group. He played a key role in the inception and development of the Intel® Xeon Phi™ coprocessor for technical computing applications by demonstrating the viability of applying Intel’s many-core graphics processor to solving technical computing problems. He led the worldwide technical enabling team for Intel Xeon Phi products, focused on porting and optimizing applications on the Xeon Phi coprocessor. With 25 years of experience in computer architecture and software design, Rahman contributes his expertise in technical code optimization, performance tuning, and processor microarchitectural analysis in the HPC domain.