PCI Express* Electrical Interconnect Design

Practical Solutions for Board-level Integration and Validation
Book Type: Intel Press Books
Table of Contents:

Intel and other companies throughout the computer and communications industries are adopting PCI Express* technology as the successor to today's Conventional PCI* and PCI-X* architectures. The PCI Express serial architecture offers scalable bandwidth and advanced features to meet the I/O needs of next-generation systems.

PCI Express* Electrical Interconnect Design is a how-to guide for system design engineers, board and layout designers, signal integrity engineers, communication high-speed designers, test engineers and technicians, and validation engineers.

With design flowcharts, example schematics, and testing checklists at your fingertips, you will learn how to translate PCI Express electrical specifications into a reliable and robust interface implementation. Topics include:

Desktop, server, workstation, mobile, and communication system designs
Modeling and simulation in both frequency and time domains
Design guidelines for layout
Validation of the final design using measurement and correlation procedures

"One can either spend a lot of time experimenting, or read this book. It offers the right level of details on the electrical guidelines. I especially find that chapters 5, 6 and 7 are a MUST READ for any hardware designers and CAD guys who want their board TO WORK!"

Eric Duchesne, P.Eng., Avnet Design Services

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About the Author(s)

Dave Coleman

Dave Coleman is a Staff Platform Application Engineer at Intel with 22 years of electrical design, modeling and simulation experience. He specializes in enabling and integration of customer Intel QuickPath Interconnect designs in Intel® Server platforms. Dave is the co-author of the book PCI Express Electrical Interconect Design published by Intel Press and has contributed articles to Printed Circuit Design magazine. Dave has previously developed platform design guidelines for PCI Express* and InfiniBand* technology platform applications, and served on the PCI Express Gen1 and Gen2 Cabling workgroups.

Mohammad Kolbehdari

Mohammad Kolbehdari is a Senior Staff Hardware Engineer at Intel involved with PCI Express interconnect design and simulation. He developed a 3D full-wave modeling methodology for high-speed bus and package design used extensively throughout Intel and is currently creating second-generation PCI Express design guidelines. Mohammad holds a PhD in Electrical Engineering and is a regular contributor to IEEE professional journals, COMPEL, and Journal of the Franklin Institute.

Scott Gardiner

Scott Gardiner is a Senior Hardware Engineer at Intel and holds a Master's degree in Electrical Engineering. Since joining Intel in 1997, Scott has made significant contributions to various high-speed interconnect and PCB designs. Involved with PCI Express since its inception, Scott was the lead engineer on one of Intel's first prototype PCI Express boards and a key contributor to Intel's first PCI Express desktop motherboard.

Stephen Peters

Stephen Peters leads a group at Intel developing methodologies for validating next generation chip and board-level interfaces for PCI Express. Over the past 15 years, Stephen has designed high-speed bus interfaces and solved signal integrity issues. From 2001 through 2003, he served as chair of the I/O Buffer Information Specification (IBIS) Open Forum and continues to be major contributor to the IBIS specification.