Weaving High Performance Multiprocessor Fabric

Architectural Insights to the Intel® QuickPath Interconnect
Book Type: Intel Press Books
Table of Contents:

Welcome to the era of the Intel® QuickPath Interconnect!

Weaving High Performance Multiprocessor Fabric is written for hardware design, validation and BIOS engineers to introduce the compelling mix of performance and features in the Intel® QuickPath Interconnect. From the foreword, Robert P. Colwell opines: "Even for inveterate geeks like me, most technical books are dry as dust and work much better than insomnia pills. They should come with warning stickers: Do not operate heavy machinery for a week after reading this book. Not this book though: Weaving High Performance Multiprocessor Fabric is engaging, educational, well-organized and directly useful. It doesn't get any better than that."

It explains the Intel QuickPath Interconnect, which provides the foundation for future generations of Intel® microprocessor systems. "With one day of reading this book, everyone familiar with the existing Front Side Bus architecture will have good visibility into what is new in the Intel QuickPath Interconnect." —Simon Czermak, Fujitsu Siemens Computers Ltd.

"Weaving High Performance Multiprocessor Fabric gives a clear view of the concepts, system features and technical details of the Intel QuickPath Interconnect."

Sophie Houssiaux, Bull

"I find that members of my team tend to focus on the details of the circuits that they are designing and can miss the "big picture." Weaving High Performance Multiprocessor Fabric certainly fills that gap and at a very readable level."

Thomas Walley, Avago Technologies

"I would distribute Weaving High Performance Multiprocessor Fabric to our hardware design engineers, debug engineers and BIOS engineers. It is valuable to the design and debug engineers who really need to have a good understanding of how things fit together and work to enable them to perform their respective tasks better. BIOS engineers need to know about such things as system initialization, error detection and handling, etc. to ensure that they get the system booting reliably."

Edward Leigh, Fujitsu Siemens Computers

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About the Author(s)

Gurbir Singh

Gurbir Singh is a Senior Principal Engineer in the Digital Enterprise Architecture and Planning group in Intel. Gurbir lead the architecture team defining the Intel QuickPath Interconnect. Gurbir has 31 years of experience in CPU and platform architecture. He joined Intel in 1984 and has worked on the architecture of several CPUs including the Intel® Pentium® Pro processor and its follow-ons: the Intel® Pentium® II, Pentium® III and Pentium® 4 processors. He was responsible for the architecture of the caches and system interfaces (the Front Side Bus) for many Intel® processors. Most recently he worked on the Intel® Core™ i7 project which introduces the Intel QuickPath Interconnect.

Robert A. Maddox

Robert A. Maddox completed his Master’s of Science in Electrical Engineering degree from Georgia Tech, then went to work on a variety of small scale computing projects with NCR Corporation. After a brief stint with Harris Corporation, Robert returned to NCR (then AT&T, then NCR again) and worked on several aspects of design, validation, and production of medium scale server systems. This included work with both the Front-Side Bus and I/O buses used in Multiprocessor servers. Robert joined Intel in 1998 and moved into working on the pre-silicon validation aspects of a server I/O hub.

Robert J. Safranek

Robert J. Safranek attained his bachelor from the University of Nebraska and masters from Portland State University. For his first ten years of his career he developed products in the area of communications, telecommunications, and high performance I/O architectures for computer systems. For the last seventeen years Robert has been developing NUMA and CC-NUMA architectures, resolving cache coherency and memory consistency issues for link based systems for Sequent, IBM, and now Intel Corp. He joined Intel in 2000 and has been working on the Intel QuickPath Interconnect definition since its inception and was the primary architect for the first Intel QPI products.